The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for manufacturing, analyzing and debugging circuitry within an integrated circuit die.
Recent technological advances in the semiconductor industry have permitted dramatic increases in circuit density and complexity, and commensurate decreases in power consumption and package sizes for integrated circuit devices. Single-chip microprocessors now include many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A byproduct of these technological advances has been an increased demand for semiconductor-based products, as well as increased demand for these products to be fast, reliable, and inexpensive. These and other demands have led to increased pressure to manufacture a large number of semiconductor devices at an efficient pace while increasing the complexity and improving the reliability of the devices.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for manufacturing, testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the possibility of manufacturing a defective device. It is also helpful to be able to perform the manufacture, testing and debugging of integrated circuits in an efficient and timely manner.
One type of circuit structure used in semiconductor devices is silicon-on insulator (SOI) structure. In typical SOI structures, an insulator layer is formed over semiconductor die substrate, and a thin layer of silicon is formed on the insulator. Source and drain regions are then formed in the silicon layer and over the insulator. One advantage of such structure is that a transistor using the source and drain regions is able to switch faster than a transistor formed using conventional methods, due to reduced capacitance in the resulting structure. However, analysis of devices that employ SOI structure is challenging because accessing source, drain or other circuit regions often requires or at least benefits from destruction of a portion of the structure. The insulator portion of the SOI structure makes this access difficult because, for example, the circuitry is formed under the SOI when approached from the back side of a flip-chip die. In addition, analysis of the die is better executed when the insulator portion is maintained intact. For these and other reasons, a method and system for analysis and repair of SOI structure in IC devices that address these challenges would be beneficial.
The present invention is directed to a method and system for accessing and analyzing circuitry in a flip-chip die having SOI structure. A particular aspect of the present invention is directed to providing the ability to access transistors and other circuit regions and to repair and/or reconstruct the accessed regions. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment, the present invention is directed to a method for analyzing a flip-chip semiconductor die having SOI structure and a circuit side opposite a back side. A focused ion beam (FIB) is directed at the back side of the die and a selected portion of substrate including a portion of the insulator of the SOI structure is removed from the die. The removed substrate exposes an insulator region in the die. A signal is coupled from a circuit portion in the circuit side of the die via the exposed region and the die is analyzed therefrom. Material is deposited in the exposed region and the selected portion of the die that had been removed is reconstructed. In this manner, access for analyzing the die is improved via the ability to couple a signal through the insulator and to repair a portion of the die that has been altered for analysis. Analysis that would otherwise be destructive can be performed and the ability of the die to function after analysis can be maintained.
In another example embodiment of the present invention, a system is adapted for analyzing a flip-chip semiconductor die having SOI structure and a circuit side opposite a back side. The system includes a FIB arrangement adapted to remove a selected portion of substrate from the die and form an exposed region that includes a portion of the insulator of the SOI structure. A testing arrangement is adapted to couple a signal from a selected circuit portion in the die via the exposed region and to analyze the die via the coupled signal. A deposition arrangement is adapted to deposit material in the exposed region and to reconstruct the selected portion of the die having been removed.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
FIG. 1 is a semiconductor die undergoing analysis, according to an example embodiment of the present invention;
FIG. 2 is the semiconductor die of FIG. 1 undergoing further analysis, according to another example embodiment of the present invention;
FIG. 3 is the semiconductor die of FIG. 2 undergoing further analysis, according to another example embodiment of the present invention;
FIG. 4 is a semiconductor die undergoing analysis, according to another example embodiment of the present invention;
FIG. 5 is a semiconductor die undergoing circuit repair, according to another example embodiment of the present invention;
FIG. 6 is a semiconductor die undergoing repair after processing, according to another example embodiment of the present invention; and
FIG. 7 is a system for analyzing a semiconductor die, according to another example embodiment of the present invention.